The present invention relates to a semiconductor device, a nonvolatile semiconductor memory, a system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including a semiconductor device or nonvolatile semiconductor memory, and an electric device with which this electric card can be used.
FIG. 22 shows the circuit configuration of a conventionally used nonvolatile semiconductor memory by taking a nonvolatile semiconductor memory as an example. This nonvolatile semiconductor memory includes a memory cell array MCA, address buffer ABF, column decoder CDC, row decoder RDC, sense amplifier S/A, fuse register FRG, I/O buffer 10BF, power-on reset circuit PORC, control circuit CT101, and voltage generation circuit VGC.
The memory cell array MCA has normal memory cell areas MC1 and MC2 for storing data, and a ROM fuse RF for storing data (to be referred to as fuse data hereinafter) required to be read out after the power source is turned on. Examples of this fuse data are replacement data for replacing defective portions in the memory cell areas MC1 and MC2 with other redundancy circuits, and trimming data for adjusting a timer and voltage generator.
Of input data to the address buffer ABF, a column address is input to and decoded by the column decoder CDC, a row address is input to and decoded by the row decoder RDC, and data write or read operation with respect to the memory cell MC1 or MC2 in the memory cell array MCA is performed at the designated address. When data is to be read out, the data is output via the sense amplifier S/A and I/O buffer 10BF. When data is to be written, the data is supplied to the memory cell array MCA via the I/O buffer IOBF. Also, the fuse data stored in the ROM fuse RF is supplied to and held in the fuse register FRG via the sense amplifier S/A and column decoder CDC.
The voltage generation circuit VGC uses an externally supplied power source voltage VCC to generate various voltages such as a reference voltage Vref and program voltage Vpg.
The power-on reset circuit PORC outputs a low-level, power-on reset signal PWONRSTn before the power source voltage reaches a power-on detection level V2 after the power source is turned on. When the power source voltage reaches this power-on detection level V2, the power-on reset circuit PORC outputs a high-level, power-on reset signal PWONRSTn to the control circuit CT101.
On the basis of this power-on reset signal PWONRSTn, the control circuit CT101 initializes the whole device, i.e., the address buffer ABF, fuse register FRG, column decoder CDC, sense amplifier S/A, row decoder RDC, and voltage generation circuit VGC, among other circuits shown in FIG. 22, by supplying an initialization control signal to these components.
To initialize the entire device, the above-mentioned fuse data stored in the ROM fuse RF must be read out and latched. If this fuse data is stored in a fuse circuit formed by a fuse which is blown by a laser, this fuse data is read. A read circuit for reading this fuse data is formed as a CMOS logic circuit. The level of a power source voltage with which this read circuit is activated is set to be equal to or higher than a voltage Vlgc at which the CMOS logic circuit starts operating.
In the nonvolatile semiconductor memory as shown in FIG. 22, however, a specific area (the ROM fuse RF) in the memory cell array MCA can be allocated as a means for storing the fuse data.
In this case, the fuse data must be read out similar to normal data when the device is initialized. So, this data is readout from the ROM fuse RF (this operation will be referred to as ROM read hereinafter).
In this operation, as shown in FIG. 23, the power-on detection level V2 must be set higher than a minimum voltage V1 at which at least read operation is possible. Assume that, in a course during which the power source is turned on and the level rises, the power source voltage reaches the minimum operating voltage V1 at which read operation is possible at time T2, ROM read is started when the power source voltage reaches the power-on detection level V2 (V2>V1) at time T3, and this read is performed from time T3 to time T4.
This ROM read is desirably performed automatically when the power source is turned on (power ON), i.e., started immediately after initialization is complete after the power source is turned on. A signal for controlling this ROM read is generated by the control circuit CT101 which receives the high-level, power-on reset signal PWONRSTn output from the power-on reset signal PORC.
For example, a circuit shown in FIG. 24 is used in this power-on reset circuit PORC. The power source voltage VCC is divided by resistors R1 and R2, and a divided level N1 is supplied to the gate of a P-channel transistor PT1. This P-channel transistor PT1, a depression type transistor DT1, and a resistor R3 are connected between a power source voltage VCC terminal and ground terminal. The potential at the connection point of the drains of the transistors PT1 and DT1 is delayed by a delay circuit INC formed by an inverter array. This delayed potential is output as the power-on reset signal PWONRSTn.
The circuit configuration of the control circuit CT101 is as shown in FIG. 25. The power-on reset signal PWONRSTn input to this control circuit CT101 is supplied to a different control circuit OCT, a pulse generator PG11, and a ROM read controller RRC.
The pulse generator PG11 supplies, to a NAND gate NA11, a signal which is obtained by inverting the power-on reset signal PWONRSTn by an inverter IN11 and delaying this inverted signal by a delay circuit DL, and the power-on reset signal PWONRSTn, thereby generating a signal which is at low level only for the delay time. An inverter IN12 inverts this signal to apply an activation pulse ROMRDSTT to a set terminal Set.
The ROM read controller RRC is reset when the power-on reset signal PWONRSTn which is input to a reset terminal/Reset is at low level after the power source is turned on. When the activation pulse ROMRDSTT is input after that, the ROM read controller RRC generates a control signal for starting ROM read, and outputs this control signal to the individual circuits for performing ROM read.
As shown in FIG. 24, fluctuations in the threshold voltage of the P-channel transistor PT1 are reflected on the generation of the power-on reset signal PWONRSTn. This varies the detected level V2 shown in FIG. 23. Accordingly, the power-on detection level V2 when the power-on reset signal PWONRSTn is to be generated is so set as to have a large margin with respect to the power source voltage specification.
Consequently, this power-on detection level V2 is set at a very low voltage near the voltage V1 at which read operation is possible. So, ROM read must be performed at a low power source voltage.
The conventional device has the following problems since ROM read is thus started near the voltage V1 at which read operation is possible.
First, when ROM read is started at a low power source voltage, this power source voltage sometimes slightly lowers owing to large current consumption required for the read operation. As a consequence, the power source voltage may become lower than the voltage V1 at which read operation is possible, and may make it impossible to accurately read out fuse data important as chip initial data. This may interfere with the subsequent operation.
Also, if, after ROM read is performed, the readout data is found to have an error due to a circuit defect, variation in the characteristics of elements forming the circuit, or fluctuation or defect in the fabrication process, this defective portion cannot be replaced with a redundancy circuit unless ROM read is executed again. This makes the whole device unusable.
If an automatic sequence is so programmed as to start ROM read again in a case like this, the result is “fail” whenever ROM read is performed, so ROM read is permanently repeated.